1. Field of the Invention
The present invention relates to a semiconductor assembly board, and more particularly to a three dimensional semiconductor assembly board, which includes a bump/flange based supporting board, a coreless build-up circuitry and a built-in electronic device.
2. Description of Related Art
High-performance three dimensional semiconductor assembly typically includes an interposer coupled to a high density interconnect substrate wherein build-up circuitry layers are deposited on both sides of a thick copper-clad-laminate core. The laminate core which is made of thick epoxy-resin-impregnated glass fiber is used to provide mechanical rigidity to the overall board.
FIG. 1 is the sectional view of a conventional three dimensional flip chip assembly wherein a laminate core is enclosed in a high density interconnect substrate 13 and an interposer 15 is mounted onto the high density interconnect substrate 13 to serve as the connection media for a flip mounted chip 17 in accordance with the prior art. Referring to FIG. 1, the high density interconnect substrate 13 comprises a core layer 131, a top and bottom build-up circuitry 132, inter-layer connection 133 (micro-via) and a plated through hole 134 that connects the build-up circuitry 132 deposited on both sides of the core.
Latest trends of electronic devices such as mobile internet devices (MIDs), multimedia devices and computer notebooks demand for faster and slimmer designs. In the frequency band of a general signal, the shorter paths of circuitry, the better the signal integrity. Thus, the size of inter-layer connection, i.e., the diameter of the micro-via and plated through hole in the substrate must be reduced in order to improve the signal delivery characteristic of the electronic component. As plated-through-hole in the copper-clad laminate core is typically formed by mechanical CNC drill, reducing its diameter in order to increase wiring density encounters seriously technical limitations and often very costly. As such, coreless substrates are proposed for packaging substrate to enable a thinner, lighter and faster design of the components. However, as coreless boards do not have a core layer to provide a necessary flexural rigidity, they are more susceptible to warpage problem when under thermal stress compared to that of conventional boards with core layers.
Furthermore, as coreless build-up circuitry removes the core layers which are normally designed for the purpose of power/ground planes as well as heat sink, electrical and thermal performances of the semiconductor device can be adversely affected especially when they are performing high frequencies transmitting or receiving of electromagnetic signals.
U.S. Pat. No. 7,435,618 to Chen et al., U.S. Pat. No. 7,517,730 to Cho, U.S. Pat. No. 7,626,270 to Chen, U.S. Pat. No. 7,754,598 to Lin et al., U.S. Pat. No. 7,851,269 to Muthukumar and U.S. Pat. No. 7,981,728 to Cho disclose various methods of forming a coreless substrate having signal delivery characteristic that is improved by eliminating the core board along with the inner through hole in the core. Since the insulating material is typically a thin epoxy or polyimide dielectric layer, even with glass fiber impregnation, their mechanical rigidity for supporting semiconductor assembly is questionable and the assembly often suffers high yield loss due to warping issue.
U.S. Pat. No. 7,164,198 to Nakamura et al., and U.S. Pat. No. 7,586,188 to Cheng disclose a coreless packaging substrate in which a re-enforcement or stiffener such as solid metal block or ceramic substrate is disposed on the surface of the coreless substrate with an opening to accommodate assembled semiconductor chip. In this approach, the re-enforcement aims to provide a critical support for the coreless build-up circuitry against warping. Although a supporting platform is created and warping issues may be resolved, etching a thick metal block or attaching a stiffener to the thin build-up circuitry is prohibitively cumbersome and prone to create many yield-loss issues such as an uncontrollable boundary line due to etching under-cut of thick metal block or bleeding of the bonding material to the cavity that would contaminate the contact pads on the coreless substrate. Furthermore, as it is difficult to accurately position the stiffener on the build-up substrate due to lateral displacement, voids and inconsistent bond lines arise between the stiffener and the coreless build-up circuitry. The assembly suffers from high yield loss, poor reliability and excessive cost.
U.S. Pat. No. 6,555,906 to Towel et al., U.S. Pat. No. 6,750,397 to Ou et al, and U.S. Pat. No. 8,058,723 to Chia disclose an assembly in which a semiconductor chip is housed in a cavity of a metal supporting frame such as a metal block before fabricating build-up circuitry. Since the cavity in the metal block is formed by etching or by micro-machining or by milling out a portion of the metal frame, the major drawbacks include low throughput. As inconsistent cavity dimension and depth control of the recess in the metal block will result in low yield, it is not suitable for high volume production. Furthermore, once the metal supporting frame is removed, the assembly will become warping again, voids and cracks at the interfaces can result in serious reliability concern.
U.S. Pat. No. 7,042,077 to Walk and U.S. Pat. No. 7,161,242 to Yamasaki et al. disclose a three-dimensional assembly in which an interposer is attached to a coreless substrate reinforced with a base material. Similar to other prior arts, the attachment of the reinforcing base can result in serious yield and reliability concerns.
In view of the various development stages and limitations in currently available three-dimensional packages for high I/O and high performance semiconductor devices, there is a need for a coreless package assembly board that can provide optimize signal integrity, adequate thermal dissipation, low warping and maintain low cost manufacturing.